View NCP81174_8375083.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2015 march, 2015 ? rev. 5 1 publication order number: NCP81174/d NCP81174 4/3/2-phase synchronous buck controller with power saving mode and pwm vid interface the NCP81174 is a general?purpose up to four ?phase synchronous buck controller. it combines differential voltage sensing, differential phase current sensing, and pwm vid interface to provide accurate regulated power for the computer or graphic controllers. it can receive power saving command (psi) fr om processors and operates in single?phase diode emulation mode to obtain high efficiency in light load. dual?edge multiphase pwm modulation ensures a fast transient response with minimum possible capacitors. features ? output voltage up to 2.0 v with pwm vid interface ? support 1.8 v and 3.3 v vid interface ? remote differential output voltage sense ? differential current sense for each phase ? 200 khz ? 1000 khz switching frequency ? power saving interface (psi) ? power good output ? thermally compensated current monitoring ? over current protection ? fast transient response ? 5 v v cc shunt regulator ? latched ovp and uvp protections ? qfn?32, 5 x 5 mm, 0.5 mm pitch package ? this is a pb?free device typical applications ? gpu and cpu power ? graphics card applications ? desktop and notebook applications device package shipping ? ordering information NCP81174mntxg qfn32 (pb?free) 2500 / tape & reel qfn32 mw suffix case 488am marking diagram www. onsemi.com a = assembly location wl = wafer lot yy = year ww = work week = pb?free package ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. (note: microdot may be in either location) 32 1 NCP81174 awlyyww 1
NCP81174 www. onsemi.com 2 1 3 5 7 2 4 6 8 10 12 14 16 11 13 15 g1 12vmon vidbuf vcc drvon g4 g3 g2 cs4 cs4n cs3 cs3n cs2 top view (not to scale) cs1 comp diffout vfb vdrp vdfb cssum vsp vsn NCP81174 cs1n cs2n flag/gnd (pin 32) 31 29 27 25 30 28 26 23 21 19 17 24 22 20 18 rosc en psi vr_rdy vref vid 9 32 refin ilim figure 1. pinout
NCP81174 www. onsemi.com 3 vr_rdy psi vid vr_en cpu gnd 12v_filter 12v_filter 12v_filter 12v_filter 12v_filter 12v_filter 12v_filter 12v_filter 12v_filter 3.3v vref vref vsp vsn vcc od in bst drh sw drl pgnd d1 c3 q1 q2 c2 l1 cs1 c4 c1 vcc od in bst drh sw drl pgnd vcc od in bst drh sw drl pgnd vcc od in bst drh sw drl pgnd + cdfb rt2 ch cf cfb1 NCP81174 4 en 3 vr_rdy 1 vidbuf 5 psi 10 vsn 9 vsp 11 diffout 12 comp 13 vfb 14 vdrp 15 vdfb 16 cssum 25 g1 18 cs1 17 cs1n 26 g2 20 cs2 19 cs2n 27 g3 22 cs3 21 cs3n 28 g4 24 cs4 23 cs4n 29 drvon 6 12vmon 30 vcc 33 gnd 7 rosc 8 ilim 32 refin 2 vid 31 vref u2 rs1 r2 r6 rnor riso1 riso2 rdrp rfb1 rfb rf rosc figure 2. typical four phase application circuit with pwm?vid interface
NCP81174 www. onsemi.com 4 cs amps ramp generator vref fault logic uvlo pgood pwm control uvp&ovp vid vidbuf refin vsn vsp diffout vfb comp vdfb vdrp cssum cs1 cs1n cs2 cs2n cs3 cs3n cs4 cs4n g1 g4 g3 g2 drvon psi rsoc 12vmon vr_rdy vref vcc gnd ilim en figure 3. functional block diagram
NCP81174 www. onsemi.com 5 pin description pin name description 1 vidbuf vid pwm pulse output from an internal buffer. 2 vid voltage id from processor. 3 vr_rdy power good indicator. 4 en chip enable. 5 psi power saving control. three levels. 6 12vmon 12 v input power rail monitor. it is a divided down voltage from the input power rail, should be kept to less than 4 v at all time. 7 rosc a resistance from this pin to ground programs the oscillator frequency. 8 ilim over current shutdown threshold setting. 9 vsp non?inverting input to the internal differential remote sense amplifier. 10 vsn inverting input to the internal differential remote sense amplifier. 11 diffout output of the differential remote voltage sense amplifier. 12 comp output of the compensation amplifier. 13 vfb inverting input of the compensation error amplifier 14 vdrp voltage signal proportional to the total current. 15 vdfb current summing amplifier inverting input 16 cssum current summing output signal 17 cs1n inverting input to current sense amplifier, phase 1. 18 cs1 non?inverting input to current sense amplifier, phase 1. 19 cs2n inverting input to current sense amplifier, phase 2. 20 cs2 non?inverting input to current sense amplifier, phase 2. 21 cs3n inverting input to current sense amplifier, phase 3. 22 cs3 non?inverting input to current sense amplifier, phase 3. 23 cs4n inverting input to current sense amplifier, phase 4. 24 cs4 non?inverting input to current sense amplifier, phase 4. 25 g1 phase 1 pwm output, 3 levels. 26 g2 phase 2 pwm output, 3 levels. 27 g3 phase 3 pwm output, 3 levels. 28 g4 phase 4 pwm output, 3 levels. 29 drvon gate driver enable. 30 vcc power supply for the chip. NCP81174 has a built?in 5 v shunt regulator, allowing it to connect to the external 12 v supply through a resistor. do not connect a 5 v supply to vcc directly. 31 vref 2.0 v output reference voltage. a 10 nf ceramic capacitor is recommended to connect this pin to ground. 32 refin reference voltage input for output voltage regulation. 33 flag thermal pad and analog ground, connected to system ground.
NCP81174 www. onsemi.com 6 maximum ratings electrical information pin symbol vmax vmin isource isink comp 5.5 v ?0.3 v 10 ma 10 ma vdrp 5.5 v ?0.3 v 5 ma 5 ma vsp 5.5 v gnd ? 300 mv 1 ma 1 ma vsn gnd + 300 mv gnd ? 300 mv 1 ma 1 ma diffout 5.5 v ?0.3 v 20 ma 20 ma vr_rdy 5.5 v ?0.3 v n/a 20 ma vcc 7.0 v ?0.3 v n/a 10 ma rosc 5.5 v ?0.3 v 1 ma n/a pwmvid 5.5 v ?0.3 v (?2 v, <50 ns) all other pins 5.5 v ?0.3 v *all signals referenced to agnd unless otherwise noted. thermal information rating symbol value unit thermal characteristic, qfn package (note 1) r thja 48.5 c/w junction temperature range (note 2) t j ?40 to 125 c operating ambient temperature range t a 0 to 100 c maximum storage temperature range t stg ?55 to +150 c moisture sensitivity level, qfn package msl 1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *the maximum package power dissipation must be observed. 1. jesd 51?5 (1s2p direct?attach method) with 0 lfm. 2. jesd 51?7 (1s2p direct?attach method) with 0 lfm.
NCP81174 www. onsemi.com 7 electrical characteristics (v vcc = 5 v, v refin = 1.0 v, v psi = 3.3 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from 0 c to 100 c. unless other noted.) characteristics test conditions symbol min typ max unit supply voltage system input voltage range v sys 7.0 20 v supply current dc supply current vsys = 13.2 v, rshunt = 150 54 60 ma uvlo turn?on current 30 35 ma vcc uvlo rising 4.9 5.2 v vcc uvlo falling 3.8 4.1 v vcc quiescent current no switching, ps0 no switching, ps1/ps2 i cc ? ? 46 46 ? ? ma ma switching frequency ps0 switching frequency range f sw 200 1000 khz switching frequency accuracy 10 % rosc output voltage 2.0 2.05 v voltage reference vref reference voltage i ref = 1 ma v vref 1.98 2.0 2.02 v pwm modulation minimum on time (note 3) fsw = 800 khz ? 3 0 ? ns 0% duty cycle comp voltage when the pwm outputs remain hi ? 1.3 ? v 100% duty cycle comp voltage when the pwm outputs remain hi ? 2.3 ? v pwm phase angle error between adjacent phases ?15 15 voltage error amplifier open?loop dc gain (note 3) 100 db unity gain bandwidth (note 3) 10 mhz slew rate (note 3) 5 v/ s comp voltage swing i comp (source) = 2 ma 3.5 ? ? v i comp (sink) = 0.2 ma ? ? 50 mv non?inverting voltage range (note 3) 0 1.3 3 v input bias current ?50 0 50 na input offset voltage (note 3) vsp = vsn = 1.0 v ?1.0 1.0 mv current?sense amplifier input bias current csx = csxn = 1.0 v ?200 0 200 na input offset voltage (note 3) ?1.0 1.0 mv common mode input range (note 3) ?0.3 2.0 v differential mode input range ?120 120 mv closed?loop dc gain (note 3) 0 v < csx ? csxn < 0.1 v 5.7 6.0 6.3 v/v ?3db gain bandwidth (note 3) 10 mhz current sharing offset ?2.5 ? 2.5 mv product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. guaranteed by design, may not be tested.
NCP81174 www. onsemi.com 8 electrical characteristics (v vcc = 5 v, v refin = 1.0 v, v psi = 3.3 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from 0 c to 100 c. unless other noted.) characteristics unit max typ min symbol test conditions current summing amplifier current sense input to cssum dc gain ?60 mv < csx ? csxn < 60 mv ?3.93 v/v current sense input to cssum ?3 db bandwidth (note 3) cl = 10 pf to gnd, rl = 10 k to gnd 4 mhz cssum output slew rate (note 3) 4 v/ s cssum summing amp output offset (note 3) ?15 0 15 mv maximum cssum output voltage 3.0 v minimum cssum output voltage 0.3 v output source current (note 3) 1 ? ? ma output sink current (note 3) 1 ? ? ma droop amplifier vdrp input bias current (note 3) ?200 200 na input offset voltage (note 3) vsp = vsn = 1.1 v ?4.0 4.0 mv open loop dc gain (note 3) cl = 20 pf to gnd including esd rl = 1 k to gnd ? 100 db open loop unity gain bandwidth (note 3) cl = 20 pf to gnd including esd rl = 1 k to gnd ? 10 ? mhz maximum output voltage i source = 4.0 ma 3 ? ? v minimum output voltage i sink = 1.0 ma ? ? 1 v output source current (note 3) vout = 3.0 v 4 ? ? ma output sink current (note 3) vout = 1.0 v 1 ? ? ma remote voltage differential sense amplifier input bias current (note 3) vsn = 0 v 30 a vsp input pull down resistance drvon = low drvon = high 1.5 17 k vsp input bias voltage (note 3) drvon = low drvon = high 0.09 0.66 v input voltage range (note 3) ?0.3 ? 3.0 v 3db bandwidth (note 3) cl = 80 pf to gnd, rl = 10 k to gnd ? 10 ? mhz closed loop dc gain vsp ?vsn = 0.5 to 1.3 v 0.98 1.0 1.025 v/v maximum output voltage i source = 2 ma 3.0 ? ? v minimum output voltage i sink = 2 ma ? ? 0.5 v output source current (note 3) vout = 3 v 2.0 ? ? ma output sink current (note 3) vout = 0.5 v 2.0 ? ? ma drvon output high voltage sourcing 500 a 3.0 ? ? v output low voltage sinking 500 a ? ? 0.7 v rise time cl (pcb) = 20 pf, vo = 10% to 90% ? 20 ? ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. guaranteed by design, may not be tested.
NCP81174 www. onsemi.com 9 electrical characteristics (v vcc = 5 v, v refin = 1.0 v, v psi = 3.3 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from 0 c to 100 c. unless other noted.) characteristics unit max typ min symbol test conditions drvon fall time cl (pcb) = 20pf, vo = 10% to 90% ? 20 ? ns enable enable threshold en rising ? 1.1 1.15 v en falling 0.95 1.0 en 3.3v io detection threshold en rising 2.5 2.55 v en falling 2.35 2.4 en input bias current external 1k pull?up to 3.3 v ? ? 1.0 a power save input psi high threshold (3.3 v input logic), refer to table 1 rising falling v highpsi_3.3v 2.05 2.4 2.2 2.55 v psi high threshold (1.8 v input logic), refer to table 2 rising falling v highpsi_1.8v 1.05 1.4 1.2 1.55 v psi low threshold rising falling v lowpsi 0.5 0.8 0.6 0.95 v psi input bias current (note 3) ? ? 1.0 a pwm outputs output high voltage sourcing 500 a 3.0 ? ? v mid output voltage 1.4 1.5 1.6 v output low voltage sinking 500 a ? ? 0.7 v rise time cl (pcb) = 50 pf, vo = 10% to 90% ? 10 15 ns fall time cl (pcb) = 50 pf, vo = 10% to 90% ? 10 15 ns 4/3/2 phase detection gate pin source current ? 80 ? ua gate pin threshold voltage 210 240 265 mv phase detect timer ? 20 27 s vr_rdy ? startup vout startup delay measured from en to vout start up from 0 v 1.3 ms vr_rdy startup delay measured from en to vr_rdy assertion 1.9 ms vr_rdy shutdown delay measured from en to vr_rdy de?assertion 200 350 ns vr_rdy low voltage i vr_rdy = 10 ma (sink) ? ? 0.4 v vr_rdy leakage current vr_rdy = 5 v ? ? 0.2 a protection ? ocp, ovp, uvp current limit ilim to vdrp gain 0.95 1.0 1.05 v/v current limit ilim to vdrp gain in psi 0.25 v/v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. guaranteed by design, may not be tested.
NCP81174 www. onsemi.com 10 electrical characteristics (v vcc = 5 v, v refin = 1.0 v, v psi = 3.3 v, typical values are referenced to t a = 25 c, min and max values are referenced to t a from 0 c to 100 c. unless other noted.) characteristics unit max typ min symbol test conditions protection ? ocp, ovp, uvp current limit ilim input range 0 2.0 v under voltage protection (uvp) threshold relative to refin voltage 50% refin under voltage protection (uvp) delay 5 s over voltage protection (ovp) threshold relative to refin voltage 150% refin over voltage protection (ovp) threshold clamping voltage 2 v over voltage protection (ovp) delay 5 us 12vmon 12vmon rising 0.94 1.0 v 12vmon falling 0.65 0.87 v 12vmon range (note 3) 4.0 v pwm?vid buffer buffer output rise time t r 3.0 ns buffer output fall time t f 3.0 ns rising and falling edge delay (note 3) t = |t r ? t f | t 0.5 ns propagation delay t pd = t phl =t plh t pd 8.0 ns propagation delay error (note 3) t pd = t phl ? t plh t pd 0.5 ns refin refin discharge switch on?resistance i refin (sink) = 2 ma 6.0 refin discharge time (note 3) measured from en assertion 100 s product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. guaranteed by design, may not be tested.
NCP81174 www. onsemi.com 11 detailed description general the NCP81174, a 4/3/2?phase synchronous buck controller with pwm vid interface in a qfn?32 package, provides a compact?footprint power management solution for new generation computing and graphic processors. it receives power saving input (psi) from processors and operates in 1?phase forced pwm or diode emulation mode to obtain high efficiency in light?load conditions. it can either receive pwmvid from the processor to achieve dynamic voltage control or locally set the reference from an internal precise 2 v regulator. operating in high switching frequency up to 1 mhz allows employing small size inductor and capacitors. introduction of dual?edge current mode multi?phase control results in fast transient response and good dynamic current balance. power operation modes the NCP81174 has three power operation modes corresponding to psi levels as shown in t able 1 and 2. the chip is compatible to different i/o systems. if the upstream controller has a 3.3 v or higher i/o interface, the configuration would follow table 1, the enable signal needs to be higher than 2.5 v to turn on the chip; if the upstream controller has a 1.8 v i/o interface, the configuration would follow table 2, the enable signal needs to be higher than 1.1 v only to turn on the chip. the operation mode can be changed on the fly. table 1. power saving interface (psi) configurations (3.3 v i/o, en > 2.5 v) psi level power mode phase configuration high (psi 2.4 v) ps0 full phase, fccm intermediate (0.8v < psi < 2.4 v) ps1 1?phase, fccm low (psi 0.8 v) ps2 1?phase, auto ccm/dcm table 2. power saving interface (psi) configurations (1.8 v i/o, 2.5 v > en > 1.1 v) psi level power mode phase configuration high (psi 1.4 v) ps0 full phase, fccm intermediate (0.8 v < psi < 1.4 v) ps1 1?phase, fccm low (psi 0.8 v) ps2 1?phase, auto ccm/dcm remote voltage sense a true differential amplifier allows the NCP81174 to measure vcore voltage feedback with respect to the vcore ground reference point by connecting the vcore reference point to vsp , and the vcore ground reference point to vsn. this configuration keeps ground potential differences between the local controller ground and the vcore ground reference point from affecting regulation of vcore between vcore and vcore ground reference points. the remote sensing amplifier also subtracts the refin (dac) voltage, thereby producing an unamplified output error voltage at the diffout pin. this output also has a 1.3 v bias voltage as the floating ground to allow both positive and negative error voltages. vsn vsp diffout refin figure 4. voltage remote sense
NCP81174 www. onsemi.com 12 switching frequency the rosc pin provides a 2.0 v reference voltage. the resistor connected to this pin will sink current from the pin to ground. this current is internally mirrored into a capacitor to create an oscillator. the period is proportional to the resistance and the frequency is inversely proportional to the total resistance. the total resistance may be estimated by equation 1. this equation is valid for the individual phase frequency in multi?phase mode ps0 and single phase mode ps1. in ps2, the frequency will be close to set frequency in ccm and scaled down with load current in dcm operation. rosc 20947 f sw ?1.1262 (eq. 1) rosc vs. freq 0 10 20 30 40 50 60 100 1000 freq?khz rosc?kohm calculation real figure 5. rosc vs. frequency pwm vid the NCP81174 receives the pwmvid signal from the upstream controller for the vcore regulation. the signal is decoded internally and passed to the vid buffer output (vidbuf), where the duty cycle is converted to a corresponding signal between 0 v and 2 v. the vidbuf high level is derived from a precise 2.0 v reference voltage. the vidbuf signal is then filtered through the external low pass filter constructed by r_refadj and c_refin. the filtered output is connected to the refin pin. the refin is the voltage reference of the vcore regulator. the output voltage maximum, minimum, and also boot voltage can be calculated with below equations. v max vref r_vref2 r vref2 r_vref1 r_refadj (eq. 2) v min vref r_vref2 r_refadj r vref1 r_vref2 r_refadj (eq. 3) v boot v max v min 2 (eq. 4) pwmvid refin vref r _refadj r _vref 1 r _vref 2 c_ refin vidbuf figure 6. pwm vid interface the NCP81174 can decode both 1.8 v and 3.3 v pwmvid output levels. if the en voltage input is more than 2.5 v, a 3.3 v pwmvid i/o is identified. if en voltage is above 1.1 v (overall chip enable threshold) but less than 2.5 v, a 1.8 v pwmvid i/o is assumed. soft start the NCP81174 has an internal controlled soft start function. the output starts to ramp up following a system reset period after the device is enabled. the device is able to
NCP81174 www. onsemi.com 13 start up smoothly under an output pre?biased condition without discharging the output before ramping up. before the output soft start begins, an internal switch will be turned on to discharge the external filter cap c_refin connected to the refin pin to reset the dac setting, the typical on resistance of the switch is around 6 s. after the discharging, internal switch will be turned off to allow external c_refin cap to recharge. after 100 s, the output voltage ramps up with a fixed slew rate of 1.3 mv/ s. the circuit can be set to start from either all the phases when the input power rails are all available or from phase 1 when only one input power rail is available by presetting the power mode from psi pin (see power operation modes). 5v shunt regulator the NCP81174 has an internal shunt regulator to generate 5 v from the external power supply (e.g. 12 v). it is recommended to connect three 0603 resistors (450 each) in parallel from a 12 v power supply to the vcc pin. thermal compensation amplifier with vdrp and vdfb pins thermal compensation amplifier is an internal amplifier in the path of droop current feedback for additional adjustment of the gain of summing current and temperature compensation. the way thermal compensation is implemented separately ensures minimum interference to the voltage loop compensation network. pwm comparators with hysteresis and 3 rd state of pwm outputs four pwm comparators receive an error signal at their non?inverting input and one of the triangle waves at its inverting input. the output of each comparator generates the pwm outputs g1, g2, g3 and g4. during the steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by vout/vin. during a transient event, both high and low comparator output transitions shift phase to the points where the error signal intersects the down and up ramp of the triangle wave. pwm signals vary between high and low in all phase operation or forced pwm mode. in power saving mode (ps2), pwm signals vary between high and mid level to allow diode emulation. 2/3/4 phase operation besides 4?phase, the part can be configured to run in 2 or 3?phase mode. in 2?phase mode, phase 1 and 3 should be used to drive the external gate drivers, gate outputs g2 and g4 should be grounded. in 3?phase mode, gate output g4 should be grounded. the current sense inputs of the unused channels should be connected to the vcore output. differential current sense amplifiers and summing amplifier four differential amplifiers are provided to sense the output current of each phase. the inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (g1, g2, g3, or g4). if a phase is unused, the differential inputs to that phase?s current sense amplifier must be shorted together and connected to the output. a voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. the outputs of four current amplifiers are fed into a summing amplifier to have a summed?up output (cssum). signal of cssum combines information of total current of all phases in operation. the gain from the total sense current input to cssum (a cssum ) is ~3.93. the output of the current sense amplifiers are used to control three functions. first, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. second, the output signal is fed to the current limit circuit. this again is the summed current of all phases in operation. finally, the individual phase current is connected to the pwm comparator. in this way current balance is accomplished. undervoltage lockout (vcc uvlo) and 12vmon vcc is constantly monitored for undervoltage lockout (uvlo). line input (normally 12v) is monitored for undervoltage lockout through 12vmon pin by connecting an appropriate resistor divider from line input to the 12vmon input. the setting of the resistor divider should make the 12vmon voltage less than 4 v at all time. during power-up, both vcc and 12vmon will be monitored. only after they exceed their individual uvlo thresholds, the full circuit will be activated and ready for soft start if the enable pin is also valid. both uvlo comparators have hysteresis to avoid chattering. the second function of 12vmon pin is to provide feed-forward input voltage information in ps2 mode, see power operation mode section. over current protection and under voltage protection a programmable overcurrent function is incorporated within the ic. the inverting input of the comparator is connected to the ilim pin. the voltage at this pin (0~2 v) sets the maximum output current the converter can produce. the vref pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. although not actually disabled, tying the ilim pin directly to the vref pin sets the limit above useful levels ? ef fectively disabling overcurrent shutdown. the comparator non?inverting input is the summed current information from the current sense amplifier. the overcurrent event will set pwm low for the rest of the cycle when the current information exceeds the voltage at the ilim pin. if the overcurrent continuously happens and the output will eventually hit the under v oltage protection (uvp) limit and it will be a latched event. the uvp limit is set to 50% below the refin voltage. the pwm outputs will stay at mid state until the v cc voltage is removed and re?applied, or the enable input is brought low and then high.
NCP81174 www. onsemi.com 14 over voltage protection an output voltage monitor is incorporated. during normal operation, if the output voltage is 50% over the refin, the vr_rdy goes low, the drvon signal remains high, and pwm outputs are set low. the limit will be clamped to 2 v if 50% over refin creates a voltage above the 2 v. the outputs will remain disabled until the v cc voltage is removed and reapplied, or the enable input is brought low and then high. design methodology programming the current limit the vref pin provides a 2.0 v reference voltage which is divided down with a resistor divider (rlim1/rlim2) and fed into the current limit pin ilim. the current limit function is based on the total sensed current of all phases multiplied by a controlled gain (acssum*adrp). dcr sensed inductor current is a function of the winding temperature. if not using thermal compensation, the best approach is to set the maximum current limit based on expected average maximum temperature of the inductor windings, dcr tmax dcr 25 ( 1 0.00393 ( t max 25 )) (eq. 5) for multiphase controller, the ripple current can be calculated as, i pp v in n v out v out l f sw v in (eq. 6) therefore calculate the current limit voltage as below, v limi a cssum a drp dcr tmax (eq. 7) i min_ocp 0.5 i pp v limit a cssum a drp dcr tmax i min_ocp 0.5 v in n v out v out l f sw v in in equation 7, a cssum and a drp are the gain of current summing amplifier and droop amplifier. + i1 i2 i3 i4 ilim acssum adrp ocp event + ? + ? riso1 riso2 rt2 rsum rnor figure 7. acssum and adrp as introduced before, v limit comes from a resistor divider connected to vref, thus v limit 2v r lim2 r lim2 r lim2 coepsi (eq. 8) a cssum
?3.93 a drp ? r nor r iso1 r iso2 r t2 r nor r iso1 r iso2 r t2 r sum (eq. 9) riso1 and riso2 are in series with r t2 , the ntc temperature sense resistor placed near inductor. rsum is the resistor connecting between pin vdfb and pin cssum. in ps0 mode, the current limit follows the equation 10; in ps1 or ps2, the current limit calculation follows equation 11, coepsi is a coef ficient for the current limiting related in power saving mode ps1, ps2. coepsi value is one over the original phase count n. refer to the psi and phase shedding section for more details. i limit (normal) 2v r lim2 r lim1 r lim2 3.93 r nor r iso1 r iso2 r t2 r nor r iso1 r iso2 r t2 r sum dcr 25 ( 1 0.00393 ( t inductor 25 )) 0.5 ( v in v out ) v out l f sw v in (eq. 10) i limit (normal) 2v r lim2 r lim1 r lim2 coepsi 3.93 r nor r iso1 r iso2 r t2 r nor r iso1 r iso2 r t2 r sum dcr 25 1 0.00393 t inductor 25 0.5 v in v out v out l f sw v in (eq. 11) n is the number of phases involved in the circuit.
NCP81174 www. onsemi.com 15 inductor current sensing compensation the NCP81174 uses the inductor current sensing method. an rc filter is selected to cancel out the impedance from inductor and recover the current information through the inductor?s dcr. this is done by matching the rc time constant of the sensing filter to the l/dcr time constant. the first cut approach is to use a 0.1 uf capacitor for c and then solve for r. r sense (t) l 0.1 f dcr 25c ( 1 0.00393 ( t 25 )) (eq. 12) because the inductor value is a function of load and inductor temperature final selection of r is best done experimentally on the bench by monitoring the vdrp pin and performing a step load test on the actual solution. compensation and output filter design vref 2.0v 0 r_vref2 0 r_vref1 c_refin r_vidbuf pwmvid 0 rsum + ? e1 e l 1 2 rdfb lbrd 1 2 dcr rbrd esrbulk eslbulk 1 2 cbulk esrcer eslcer 1 2 ccer comp 12 0 refin vramp_min voffset voff rfb rfb1 rf cfb1 ch cf r12 1e4 r6 c4 c6 0 v3 0 0 0 r14 0 0 1e4 0 r8 c5 voff vout vdrp v4 voff figure 8. system average model a simple state average model shown in figure 8 can be used to assist the system design and determine a stable solution. the goal is to compensate the system such that the resulting gain generates constant output impedance from dc up to the frequency where the ceramic takes over holding the impedance below the target output impedance. by matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter. 1 2 cf rf 1 2 ( rbrd esrbulk ) cbulk (eq. 13) 1 2 cfb1 ( rfb1 rfb ) 1 2 ccer ( rbrd esrbulk ) (eq. 14) droop injection and thermal compensation the vdrp signal is generated by summing the sensed output currents for each phase. a droop amplifier is added to adjust the total gain to approximately eight. vdrp is
NCP81174 www. onsemi.com 16 externally summed into the feedback network by the resistor rdrp. this introduces an offset which is proportional to the output current thereby forcing a controlled, resistive output impedance. + ? 1.3 v cfb1 ch rfb1 rfb rf error amp + + csx + ? gain = 1 droop amp + ? pwm comparator cf riso2 riso1 rsx rdrp rl i bias + ? gain = 4 1.3 v rsum rnor + ? 1.3 v rt cssum amp figure 9. droop injection and thermal compensation rdrp determines the target output impedance by the basic equation: v out i out z out r fb dcr a ccsum a drp r drp (eq. 15) r drp r fb dcr a cssum a drp z out (eq. 16) the value of the inductor?s dcr is a function of temperature according to equation 17: dcr(t) dcr 25c ( 1 0.00393 ( t 25 )) (eq. 17) actual dcr increases by temperature. the system can be thermally compensated to cancel this effect to a great degree by adding an ntc in parallel with rnor to reduce the droop gain as the temperature increases. the ntc device is nonlinear. putting a resistor in series with the ntc helps make the device appear more linear with temperature. the series resistor is split and inserted on both sides of the ntc to reduce noise injection into the feedback loop. the recommended total value for riso1 plus riso2 is approximately 1.0 k . the output impedance varies with inductor temperature by the equation: z out (t) r fb dcr 25c ( 1 0.00393 ( t 25 )) a cssum a drp r drp (eq. 18) by including the ntc rt2 and the series isolation resistors the new equation becomes: z out (t) r fb dcr 25c ( 1 0.00393 ( t 25 )) a cssum r nor r iso1 r iso2 r t2 r nor r iso1 r iso2 r t2 r sum r drp (eq. 19) the typical equation of an ntc is based on a curve fit equation 20: rt2 ( t ) rt2 25c e 1 273 t 1 298 (eq. 20) figure 10 shows an example of the comparison of the compensated output impedance and uncompensated output impedance varying with temperature. zout vs temperature 0.0006 0.0007 0.0008 0.0009 0.001 0.0011 0.0012 0.0013 25 45 65 85 105 celsius ohm zout zout(uncomp) figure 10. zout vs. temperature (10 k ntc with a value of 3740)
NCP81174 www. onsemi.com 17 system timing diagram figure 11. system timing diagram vsp?vsn 12v, vsys 5v, vcc en pwmvid, 1v vrrdy drvon ~700 us refin 1.1ms ~100 us vboot 3.3v or 1.8v vboot
NCP81174 www. onsemi.com 18 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCP81174/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

▲Up To Search▲

Price & Availability of NCP81174

	To Download NCP81174 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .